The present invention relates to design structures, such as design structures embodied in a machine-readable medium used in a design process, the design structure including circuits, devices and methods for transmitting signals along conductors, especially transmission lines.
Transmission lines are frequently provided by pairs of conductors used to carry signals between one integrated circuit (“IC”) or “chip” and another chip, e.g., as provided on a circuit board or wiring substrate. A transmission line has a signal conductor, e.g., a wire, or conductive trace, which is typically maintained at a constant or nearly constant spacing with respect to a ground conductor or other reference conductor. For example, a transmission line can include a first signal-carrying wire held at a constant spacing relative to a ground plane in the case of a microstrip line. In another example, a conductive sheathing forms the reference conductor, such as in the case of a coaxial cable.
In a particular example, transmission lines are provided as a combination of wiring and ground conductors used to transmit signals from one location to another within a single chip. Signals transmitted on transmission lines appear as waves in which voltage and current vary with respect to time and also vary with respect to position along the transmission line. Microelectronic circuits used in today's advanced systems, especially those designed to transmit or receive signals from transmission lines, are particularly sensitive to signal return loss. Signal return loss can be understood in terms of the propagation of voltage and/or current waves along transmission lines.
Characteristic impedance of a transmission line can transition sharply at a boundary between a transmission line and signal-receiving equipment. Sharp changes in the characteristic impedance can cause voltage and current wave signal energy to be reflected. Signal return loss is a measure of the reflection of signal energy at such boundary between a transmission line and an interface therefrom. Signal return loss can be expressed as a ratio of the magnitude of the reflected voltage wave to the magnitude of the voltage wave arriving from the transmission line. Communications-receiving circuits are particularly sensitive to signal return loss at interfaces between transmission channels and front-end interfaces of receiving circuits. This is particularly true of circuitry such as that used in signal transmitting and receiving circuits designed to operate at radio frequencies. In some communications systems known as “SerDes” (serializer-deserializer) circuits, serialized communication signals are transmitted on transmission lines at rates up to many gigabits per second (Gbs). One particular type of SerDes circuits are provided in “HSS” (high-speed SerDes) cores of certain integrated circuits or “chips”.
Providing well-matched terminations to transmission lines at the interfaces to the transmission lines is one way that signal return loss can be reduced. However, achieving well-matched terminations can be problematic. In some types of devices, particularly devices designed to receive signals from relatively long external transmission lines, such as high-speed SerDes circuits, loading of the critical wiring paths at the input interface can be a significant contributor to signal return loss. “Loading” refers to the various sources of impedance which, in the aggregate, determine the characteristic impedance presented by the signal-receiving equipment at the input interface thereof.
In an HSS core, capacitance due to the wiring along the critical paths of the interface contributes heavily to the loading. In some cases, some loading is inevitable at an input interface to signal-receiving circuits of an HSS core. Multiple circuits need to be present at the input interface of an HSS core.
Such loading is best seen in FIG. 1. That figure provides a block and schematic diagram of circuitry 100 according to the prior art which is provided at an interface to a transmission line. Such circuitry and transmission line can be provided as an element of a chip; for example, as transmitting or receiving circuitry used to transmit or receive a signal on a chip itself, e.g., for transmission of data and/or clock or control signals. Alternatively, such circuitry and transmission line can be provided in communications handling circuitry 100 which forms a part or all of front end circuitry of a receiver. According to yet another alternative, FIG. 1 is illustrative of part or all of circuitry at an external interface of a transmitter.
For purposes of illustration, it will be assumed that the communications apparatus 100 is front end circuitry of a receiver. A communication signal is input to such apparatus at input terminal 102. A first circuit block A (120) is interposed between the input terminal and an internal node N1 (122). A second circuit block B (130) is interposed between the node N1 and an internal node N2 (132). A third circuit block C (140) is interposed between node N2 (132) and the output (142) of the communications handling circuitry (100). The first, second and third circuit blocks typically either condition or modify the communication signal inputted to the communications handling circuitry 100. Alternatively, one or more of these circuit blocks functions to protect the communications circuitry against a harmful overvoltage condition at the input terminal 102, e.g., to prevent electro-static discharge (“ESD”).
The circuit blocks A, B and C lie in a sequential communication path referred to as a “critical path”, because the communication signal is transferred between circuit blocks under conditions which must best preserve its quality. In addition to these circuit blocks, the communications circuitry 100 also includes a one or more signal-handling elements D1 (150), D2 (160), and D3 (170), which are arranged to perform functions in response to the communication signal, i.e., the communication signal as exists at internal node N2.
The layout of communications circuitry shown in FIG. 1 is illustrative of the relative sizes of the above-described circuit blocks and wiring that connects them together in an integrated circuit (“IC”) or “chip”. Due to limited space on the chip, especially along the critical path, the additional signal-handling elements have to be placed relatively far from input terminal 102 of the communications circuitry. However, such layout impacts the quality of the signal ultimately output at terminal 142 by the communications handling circuitry. Significant loading of the critical communication path results from the long wiring 134 that links the added signal-handling elements 150, 160 and 170 to node N2. Such loading, in addition to junction and gate capacitance, inherently degrades the signal integrity in the HSS core. Typically, a specification for a communication standard sets a maximum limit for signal return loss. For example, the specification for the “10 Gigabit Ethernet Attachment Unit Interface” (“XAUI”) standard limits the maximum return loss to −10 dB for signal transmission frequencies above about 100 MHz. This tolerance remains at least as strict for much higher signal transmission frequencies. For example, the maximum return loss remains limited to −10 dB even at a signal transmission frequency of 2.5 GHz, i.e., at a transmission rate ranging to about 5 Gbs. To meet this standard at a transmission frequency of 2.5 GHz, the maximum parasitic capacitance that can be tolerated is about 0.85 pF, even when it is assumed that the 50 ohm transmission line is terminated in an impedance which perfectly matches its impedance.
U.S. Pat. No. 6,380,791 to Gupta et al. describes a method to reduce loading on a specific node attached to a switch used for tuning a resistive network. In such method, the switch is modified into a segmented switch, or switch resistor network is modified into tree-like segment switch to reduce loading on the specific node. However, Gupta et al. does not deal with capacitive loading at an input or output interface of communications transmission or receiving equipment.